Discussion:
[EE] Bypass capacitor really required?
Electron
2017-12-02 18:18:48 UTC
Permalink
Hello,
it may seem a banal question, but as it's the first time I use an external
oscillator (with integrated crystal), I am not sure. The datasheet makes no
mention whatsoever to the need to use a bypass capacitor in the power line:

https://global.kyocera.com/prdct/electro/product/pdf/clock_k_e.pdf

But is this truly the case?

Should I put a (100nF?) bypass capacitor anyway in your opinion?

Space on the board may be used for something else otherwise, so I don't
want to put useless components. But then again who does.

Also, I guess there's no advantage in grounding the metalcase on this
integrated oscillator, like I use to do with Xtals. Maybe it's already
grounded but I haven't received it yet.. I ask in case it's not.

Thank you.

Kind regards,
Mario

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
Jason White
2017-12-02 19:36:50 UTC
Permalink
I would highly recommend using a bypass capacitor, 100nF ceramic is fine.
Chances are is that it will work, to some degree, without it.

Needless to say: without a bypass capacitor your device could work
marginally, ie. it works one day and the next day it quits. If you value
time/reliability more than components/space then the capacitor is a good
idea.

Datasheet suggest that the case is already connected to ground.

On Sat, Dec 2, 2017 at 1:18 PM, Electron <***@infinito.it> wrote:

>
> Hello,
> it may seem a banal question, but as it's the first time I use an external
> oscillator (with integrated crystal), I am not sure. The datasheet makes no
> mention whatsoever to the need to use a bypass capacitor in the power line:
>
> https://global.kyocera.com/prdct/electro/product/pdf/clock_k_e.pdf
>
> But is this truly the case?
>
> Should I put a (100nF?) bypass capacitor anyway in your opinion?
>
> Space on the board may be used for something else otherwise, so I don't
> want to put useless components. But then again who does.
>
> Also, I guess there's no advantage in grounding the metalcase on this
> integrated oscillator, like I use to do with Xtals. Maybe it's already
> grounded but I haven't received it yet.. I ask in case it's not.
>
> Thank you.
>
> Kind regards,
> Mario
>
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>



--
Jason White
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
Jean-Paul Louis
2017-12-02 21:12:10 UTC
Permalink
Mario,
Decoupling power line of oscillators is almost mandatory. A lousy power
line will degrade severely the phase noise. Decoupling might vary with
frequency used. I'll suggest 1 microFarad in parallel with 10 nF.
But that's just me.

Good luck with your design,
Jean-Paul
N1JPL

On Dec 2, 2017 1:20 PM, "Electron" <***@infinito.it> wrote:

>
> Hello,
> it may seem a banal question, but as it's the first time I use an external
> oscillator (with integrated crystal), I am not sure. The datasheet makes no
> mention whatsoever to the need to use a bypass capacitor in the power line:
>
> https://global.kyocera.com/prdct/electro/product/pdf/clock_k_e.pdf
>
> But is this truly the case?
>
> Should I put a (100nF?) bypass capacitor anyway in your opinion?
>
> Space on the board may be used for something else otherwise, so I don't
> want to put useless components. But then again who does.
>
> Also, I guess there's no advantage in grounding the metalcase on this
> integrated oscillator, like I use to do with Xtals. Maybe it's already
> grounded but I haven't received it yet.. I ask in case it's not.
>
> Thank you.
>
> Kind regards,
> Mario
>
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
Richard Pope
2017-12-02 23:15:59 UTC
Permalink
Mario,
Yes! I won't go in to the reasons why. I bypass the Oscillator
and/or oscillators and all of the digital ICs. Linear VRs are also
bypassed but look at the datasheet to get the proper values. I mostly
use 0.1uF 50V Ceramics. I have at times used 0.01uF 50V Ceramics.
Thanks,
rich!

On 12/2/2017 12:18 PM, Electron wrote:
> Hello,
> it may seem a banal question, but as it's the first time I use an external
> oscillator (with integrated crystal), I am not sure. The datasheet makes no
> mention whatsoever to the need to use a bypass capacitor in the power line:
>
> https://global.kyocera.com/prdct/electro/product/pdf/clock_k_e.pdf
>
> But is this truly the case?
>
> Should I put a (100nF?) bypass capacitor anyway in your opinion?
>
> Space on the board may be used for something else otherwise, so I don't
> want to put useless components. But then again who does.
>
> Also, I guess there's no advantage in grounding the metalcase on this
> integrated oscillator, like I use to do with Xtals. Maybe it's already
> grounded but I haven't received it yet.. I ask in case it's not.
>
> Thank you.
>
> Kind regards,
> Mario
>


---
This email has been checked for viruses by Avast antivirus software.
https://www.avast.com/antivirus

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
Electron
2017-12-03 05:11:42 UTC
Permalink
Thank you for all replies. I would like to address one in particular:

Just one question, why 50V? Just because it's very difficult to find 100nF
ceramic capacitors of lower voltage, or 50V specification is truly needed
(but why? it's a 3.3V circuit after all).

Thank you.

Have a nice sunday,
Mario


At 00:15 2017-12-03, Richard Pope wrote:
>Mario,
> Yes! I won't go in to the reasons why. I bypass the Oscillator
>and/or oscillators and all of the digital ICs. Linear VRs are also
>bypassed but look at the datasheet to get the proper values. I mostly
>use 0.1uF 50V Ceramics. I have at times used 0.01uF 50V Ceramics.
>Thanks,
>rich!
>
>On 12/2/2017 12:18 PM, Electron wrote:
>> Hello,
>> it may seem a banal question, but as it's the first time I use an external
>> oscillator (with integrated crystal), I am not sure. The datasheet makes no
>> mention whatsoever to the need to use a bypass capacitor in the power line:
>>
>> https://global.kyocera.com/prdct/electro/product/pdf/clock_k_e.pdf
>>
>> But is this truly the case?
>>
>> Should I put a (100nF?) bypass capacitor anyway in your opinion?
>>
>> Space on the board may be used for something else otherwise, so I don't
>> want to put useless components. But then again who does.
>>
>> Also, I guess there's no advantage in grounding the metalcase on this
>> integrated oscillator, like I use to do with Xtals. Maybe it's already
>> grounded but I haven't received it yet.. I ask in case it's not.
>>
>> Thank you.
>>
>> Kind regards,
>> Mario
>>
>
>
>---
>This email has been checked for viruses by Avast antivirus software.
>https://www.avast.com/antivirus
>
>--
>http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
>View/change your membership options at
>http://mailman.mit.edu/mailman/listinfo/piclist

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
Richard Pope
2017-12-03 05:22:35 UTC
Permalink
Mario,
It could be as low as double the voltage that it is bypassing but
the 50V ones are easier to find and very common.
Thanks,
rich!

On 12/2/2017 11:11 PM, Electron wrote:
> Thank you for all replies. I would like to address one in particular:
>
> Just one question, why 50V? Just because it's very difficult to find 100nF
> ceramic capacitors of lower voltage, or 50V specification is truly needed
> (but why? it's a 3.3V circuit after all).
>
> Thank you.
>
> Have a nice sunday,
> Mario
>
>
> At 00:15 2017-12-03, Richard Pope wrote:
>> Mario,
>> Yes! I won't go in to the reasons why. I bypass the Oscillator
>> and/or oscillators and all of the digital ICs. Linear VRs are also
>> bypassed but look at the datasheet to get the proper values. I mostly
>> use 0.1uF 50V Ceramics. I have at times used 0.01uF 50V Ceramics.
>> Thanks,
>> rich!
>>
>> On 12/2/2017 12:18 PM, Electron wrote:
>>> Hello,
>>> it may seem a banal question, but as it's the first time I use an external
>>> oscillator (with integrated crystal), I am not sure. The datasheet makes no
>>> mention whatsoever to the need to use a bypass capacitor in the power line:
>>>
>>> https://global.kyocera.com/prdct/electro/product/pdf/clock_k_e.pdf
>>>
>>> But is this truly the case?
>>>
>>> Should I put a (100nF?) bypass capacitor anyway in your opinion?
>>>
>>> Space on the board may be used for something else otherwise, so I don't
>>> want to put useless components. But then again who does.
>>>
>>> Also, I guess there's no advantage in grounding the metalcase on this
>>> integrated oscillator, like I use to do with Xtals. Maybe it's already
>>> grounded but I haven't received it yet.. I ask in case it's not.
>>>
>>> Thank you.
>>>
>>> Kind regards,
>>> Mario
>>>
>>
>> ---
>> This email has been checked for viruses by Avast antivirus software.
>> https://www.avast.com/antivirus
>>
>> --
>> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
>> View/change your membership options at
>> http://mailman.mit.edu/mailman/listinfo/piclist

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
Electron
2017-12-03 10:53:45 UTC
Permalink
Thanks for clearing that. Have a nice sunday.


At 06:22 2017-12-03, Richard Pope wrote:
>Mario,
> It could be as low as double the voltage that it is bypassing but
>the 50V ones are easier to find and very common.
>Thanks,
>rich!
>
>On 12/2/2017 11:11 PM, Electron wrote:
>> Thank you for all replies. I would like to address one in particular:
>>
>> Just one question, why 50V? Just because it's very difficult to find 100nF
>> ceramic capacitors of lower voltage, or 50V specification is truly needed
>> (but why? it's a 3.3V circuit after all).
>>
>> Thank you.
>>
>> Have a nice sunday,
>> Mario
>>
>>
>> At 00:15 2017-12-03, Richard Pope wrote:
>>> Mario,
>>> Yes! I won't go in to the reasons why. I bypass the Oscillator
>>> and/or oscillators and all of the digital ICs. Linear VRs are also
>>> bypassed but look at the datasheet to get the proper values. I mostly
>>> use 0.1uF 50V Ceramics. I have at times used 0.01uF 50V Ceramics.
>>> Thanks,
>>> rich!
>>>
>>> On 12/2/2017 12:18 PM, Electron wrote:
>>>> Hello,
>>>> it may seem a banal question, but as it's the first time I use an external
>>>> oscillator (with integrated crystal), I am not sure. The datasheet makes no
>>>> mention whatsoever to the need to use a bypass capacitor in the power line:
>>>>
>>>> https://global.kyocera.com/prdct/electro/product/pdf/clock_k_e.pdf
>>>>
>>>> But is this truly the case?
>>>>
>>>> Should I put a (100nF?) bypass capacitor anyway in your opinion?
>>>>
>>>> Space on the board may be used for something else otherwise, so I don't
>>>> want to put useless components. But then again who does.
>>>>
>>>> Also, I guess there's no advantage in grounding the metalcase on this
>>>> integrated oscillator, like I use to do with Xtals. Maybe it's already
>>>> grounded but I haven't received it yet.. I ask in case it's not.
>>>>
>>>> Thank you.
>>>>
>>>> Kind regards,
>>>> Mario
>>>>
>>>
>>> ---
>>> This email has been checked for viruses by Avast antivirus software.
>>> https://www.avast.com/antivirus
>>>
>>> --
>>> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
>>> View/change your membership options at
>>> http://mailman.mit.edu/mailman/listinfo/piclist
>
>--
>http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
>View/change your membership options at
>http://mailman.mit.edu/mailman/listinfo/piclist

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
Jason White
2017-12-03 13:13:17 UTC
Permalink
The effective capacitance of general purpose ceramic capacitors is a
function of the DC voltage across it. In many cases the capacitance can
drop to less than half of the rated capacitance when you get near the
voltage rating of the part.

The severity of this effect is highly dependant on the specific type of
ceramic capacitor you have - X7R, Y5V, C0G, etc.

For decoupling a 50V part will typically perform "better" than a 6.3V one
of the same type and rating.

See muRata's explanation:
https://www.murata.com/en-us/support/faqs/products/capacitor/mlcc/char/0005

Relevant stackoverflow post "How to derate a ceramic capacitor for DC
bias":
https://electronics.stackexchange.com/questions/280719/how-to-derate-a-ceramic-capacitor-for-dc-bias

On Sunday, December 3, 2017, Electron <***@infinito.it> wrote:

>
> Thank you for all replies. I would like to address one in particular:
>
> Just one question, why 50V? Just because it's very difficult to find 100nF
> ceramic capacitors of lower voltage, or 50V specification is truly needed
> (but why? it's a 3.3V circuit after all).
>
> Thank you.
>
> Have a nice sunday,
> Mario
>
>
> At 00:15 2017-12-03, Richard Pope wrote:
> >Mario,
> > Yes! I won't go in to the reasons why. I bypass the Oscillator
> >and/or oscillators and all of the digital ICs. Linear VRs are also
> >bypassed but look at the datasheet to get the proper values. I mostly
> >use 0.1uF 50V Ceramics. I have at times used 0.01uF 50V Ceramics.
> >Thanks,
> >rich!
> >
> >On 12/2/2017 12:18 PM, Electron wrote:
> >> Hello,
> >> it may seem a banal question, but as it's the first time I use an
> external
> >> oscillator (with integrated crystal), I am not sure. The datasheet
> makes no
> >> mention whatsoever to the need to use a bypass capacitor in the power
> line:
> >>
> >> https://global.kyocera.com/prdct/electro/product/pdf/clock_k_e.pdf
> >>
> >> But is this truly the case?
> >>
> >> Should I put a (100nF?) bypass capacitor anyway in your opinion?
> >>
> >> Space on the board may be used for something else otherwise, so I don't
> >> want to put useless components. But then again who does.
> >>
> >> Also, I guess there's no advantage in grounding the metalcase on this
> >> integrated oscillator, like I use to do with Xtals. Maybe it's already
> >> grounded but I haven't received it yet.. I ask in case it's not.
> >>
> >> Thank you.
> >>
> >> Kind regards,
> >> Mario
> >>
> >
> >
> >---
> >This email has been checked for viruses by Avast antivirus software.
> >https://www.avast.com/antivirus
> >
> >--
> >http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> >View/change your membership options at
> >http://mailman.mit.edu/mailman/listinfo/piclist
>
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>


--
Jason White
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
Electron
2017-12-03 13:50:09 UTC
Permalink
I didn't know this, and it's very interesting, thank you.


At 14:13 2017-12-03, Jason White wrote:
>The effective capacitance of general purpose ceramic capacitors is a
>function of the DC voltage across it. In many cases the capacitance can
>drop to less than half of the rated capacitance when you get near the
>voltage rating of the part.
>
>The severity of this effect is highly dependant on the specific type of
>ceramic capacitor you have - X7R, Y5V, C0G, etc.
>
>For decoupling a 50V part will typically perform "better" than a 6.3V one
>of the same type and rating.
>
>See muRata's explanation:
>https://www.murata.com/en-us/support/faqs/products/capacitor/mlcc/char/0005
>
>Relevant stackoverflow post "How to derate a ceramic capacitor for DC
>bias":
>https://electronics.stackexchange.com/questions/280719/how-to-derate-a
>-ceramic-capacitor-for-dc-bias
>
>On Sunday, December 3, 2017, Electron <***@infinito.it> wrote:
>
>>
>> Thank you for all replies. I would like to address one in particular:
>>
>> Just one question, why 50V? Just because it's very difficult to find 100nF
>> ceramic capacitors of lower voltage, or 50V specification is truly needed
>> (but why? it's a 3.3V circuit after all).
>>
>> Thank you.
>>
>> Have a nice sunday,
>> Mario
>>
>>
>> At 00:15 2017-12-03, Richard Pope wrote:
>> >Mario,
>> > Yes! I won't go in to the reasons why. I bypass the Oscillator
>> >and/or oscillators and all of the digital ICs. Linear VRs are also
>> >bypassed but look at the datasheet to get the proper values. I mostly
>> >use 0.1uF 50V Ceramics. I have at times used 0.01uF 50V Ceramics.
>> >Thanks,
>> >rich!
>> >
>> >On 12/2/2017 12:18 PM, Electron wrote:
>> >> Hello,
>> >> it may seem a banal question, but as it's the first time I use an
>> external
>> >> oscillator (with integrated crystal), I am not sure. The datasheet
>> makes no
>> >> mention whatsoever to the need to use a bypass capacitor in the power
>> line:
>> >>
>> >> https://global.kyocera.com/prdct/electro/product/pdf/clock_k_e.pdf
>> >>
>> >> But is this truly the case?
>> >>
>> >> Should I put a (100nF?) bypass capacitor anyway in your opinion?
>> >>
>> >> Space on the board may be used for something else otherwise, so I don't
>> >> want to put useless components. But then again who does.
>> >>
>> >> Also, I guess there's no advantage in grounding the metalcase on this
>> >> integrated oscillator, like I use to do with Xtals. Maybe it's already
>> >> grounded but I haven't received it yet.. I ask in case it's not.
>> >>
>> >> Thank you.
>> >>
>> >> Kind regards,
>> >> Mario
>> >>
>> >
>> >
>> >---
>> >This email has been checked for viruses by Avast antivirus software.
>> >https://www.avast.com/antivirus
>> >
>> >--
>> >http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
>> >View/change your membership options at
>> >http://mailman.mit.edu/mailman/listinfo/piclist
>>
>> --
>> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
>> View/change your membership options at
>> http://mailman.mit.edu/mailman/listinfo/piclist
>>
>
>
>--
>Jason White
>--
>http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
>View/change your membership options at
>http://mailman.mit.edu/mailman/listinfo/piclist

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
Clint Jay
2017-12-03 14:44:53 UTC
Permalink
Learn something every day, thanks people.

On 3 Dec 2017 13:51, "Electron" <***@infinito.it> wrote:

>
> I didn't know this, and it's very interesting, thank you.
>
>
> At 14:13 2017-12-03, Jason White wrote:
> >The effective capacitance of general purpose ceramic capacitors is a
> >function of the DC voltage across it. In many cases the capacitance can
> >drop to less than half of the rated capacitance when you get near the
> >voltage rating of the part.
> >
> >The severity of this effect is highly dependant on the specific type of
> >ceramic capacitor you have - X7R, Y5V, C0G, etc.
> >
> >For decoupling a 50V part will typically perform "better" than a 6.3V one
> >of the same type and rating.
> >
> >See muRata's explanation:
> >https://www.murata.com/en-us/support/faqs/products/
> capacitor/mlcc/char/0005
> >
> >Relevant stackoverflow post "How to derate a ceramic capacitor for DC
> >bias":
> >https://electronics.stackexchange.com/questions/280719/how-to-derate-a
> >-ceramic-capacitor-for-dc-bias
> >
> >On Sunday, December 3, 2017, Electron <***@infinito.it> wrote:
> >
> >>
> >> Thank you for all replies. I would like to address one in particular:
> >>
> >> Just one question, why 50V? Just because it's very difficult to find
> 100nF
> >> ceramic capacitors of lower voltage, or 50V specification is truly
> needed
> >> (but why? it's a 3.3V circuit after all).
> >>
> >> Thank you.
> >>
> >> Have a nice sunday,
> >> Mario
> >>
> >>
> >> At 00:15 2017-12-03, Richard Pope wrote:
> >> >Mario,
> >> > Yes! I won't go in to the reasons why. I bypass the Oscillator
> >> >and/or oscillators and all of the digital ICs. Linear VRs are also
> >> >bypassed but look at the datasheet to get the proper values. I mostly
> >> >use 0.1uF 50V Ceramics. I have at times used 0.01uF 50V Ceramics.
> >> >Thanks,
> >> >rich!
> >> >
> >> >On 12/2/2017 12:18 PM, Electron wrote:
> >> >> Hello,
> >> >> it may seem a banal question, but as it's the first time I use an
> >> external
> >> >> oscillator (with integrated crystal), I am not sure. The datasheet
> >> makes no
> >> >> mention whatsoever to the need to use a bypass capacitor in the power
> >> line:
> >> >>
> >> >> https://global.kyocera.com/prdct/electro/product/pdf/clock_k_e.pdf
> >> >>
> >> >> But is this truly the case?
> >> >>
> >> >> Should I put a (100nF?) bypass capacitor anyway in your opinion?
> >> >>
> >> >> Space on the board may be used for something else otherwise, so I
> don't
> >> >> want to put useless components. But then again who does.
> >> >>
> >> >> Also, I guess there's no advantage in grounding the metalcase on this
> >> >> integrated oscillator, like I use to do with Xtals. Maybe it's
> already
> >> >> grounded but I haven't received it yet.. I ask in case it's not.
> >> >>
> >> >> Thank you.
> >> >>
> >> >> Kind regards,
> >> >> Mario
> >> >>
> >> >
> >> >
> >> >---
> >> >This email has been checked for viruses by Avast antivirus software.
> >> >https://www.avast.com/antivirus
> >> >
> >> >--
> >> >http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> >> >View/change your membership options at
> >> >http://mailman.mit.edu/mailman/listinfo/piclist
> >>
> >> --
> >> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> >> View/change your membership options at
> >> http://mailman.mit.edu/mailman/listinfo/piclist
> >>
> >
> >
> >--
> >Jason White
> >--
> >http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> >View/change your membership options at
> >http://mailman.mit.edu/mailman/listinfo/piclist
>
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
Richard Pope
2017-12-03 23:49:00 UTC
Permalink
Jason,
I just learned something new. It has been a good day.
Thanks,
rich!

On 12/3/2017 7:13 AM, Jason White wrote:
> The effective capacitance of general purpose ceramic capacitors is a
> function of the DC voltage across it. In many cases the capacitance can
> drop to less than half of the rated capacitance when you get near the
> voltage rating of the part.
>
> The severity of this effect is highly dependant on the specific type of
> ceramic capacitor you have - X7R, Y5V, C0G, etc.
>
> For decoupling a 50V part will typically perform "better" than a 6.3V one
> of the same type and rating.
>
> See muRata's explanation:
> https://www.murata.com/en-us/support/faqs/products/capacitor/mlcc/char/0005
>
> Relevant stackoverflow post "How to derate a ceramic capacitor for DC
> bias":
> https://electronics.stackexchange.com/questions/280719/how-to-derate-a-ceramic-capacitor-for-dc-bias
>
> On Sunday, December 3, 2017, Electron <***@infinito.it> wrote:
>
>> Thank you for all replies. I would like to address one in particular:
>>
>> Just one question, why 50V? Just because it's very difficult to find 100nF
>> ceramic capacitors of lower voltage, or 50V specification is truly needed
>> (but why? it's a 3.3V circuit after all).
>>
>> Thank you.
>>
>> Have a nice sunday,
>> Mario
>>
>>
>> At 00:15 2017-12-03, Richard Pope wrote:
>>> Mario,
>>> Yes! I won't go in to the reasons why. I bypass the Oscillator
>>> and/or oscillators and all of the digital ICs. Linear VRs are also
>>> bypassed but look at the datasheet to get the proper values. I mostly
>>> use 0.1uF 50V Ceramics. I have at times used 0.01uF 50V Ceramics.
>>> Thanks,
>>> rich!
>>>
>>> On 12/2/2017 12:18 PM, Electron wrote:
>>>> Hello,
>>>> it may seem a banal question, but as it's the first time I use an
>> external
>>>> oscillator (with integrated crystal), I am not sure. The datasheet
>> makes no
>>>> mention whatsoever to the need to use a bypass capacitor in the power
>> line:
>>>> https://global.kyocera.com/prdct/electro/product/pdf/clock_k_e.pdf
>>>>
>>>> But is this truly the case?
>>>>
>>>> Should I put a (100nF?) bypass capacitor anyway in your opinion?
>>>>
>>>> Space on the board may be used for something else otherwise, so I don't
>>>> want to put useless components. But then again who does.
>>>>
>>>> Also, I guess there's no advantage in grounding the metalcase on this
>>>> integrated oscillator, like I use to do with Xtals. Maybe it's already
>>>> grounded but I haven't received it yet.. I ask in case it's not.
>>>>
>>>> Thank you.
>>>>
>>>> Kind regards,
>>>> Mario
>>>>
>>>
>>> ---
>>> This email has been checked for viruses by Avast antivirus software.
>>> https://www.avast.com/antivirus
>>>
>>> --
>>> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
>>> View/change your membership options at
>>> http://mailman.mit.edu/mailman/listinfo/piclist
>> --
>> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
>> View/change your membership options at
>> http://mailman.mit.edu/mailman/listinfo/piclist
>>
>

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
a***@stfc.ac.uk
2017-12-03 13:17:56 UTC
Permalink
> Thank you for all replies. I would like to address one in particular:
>
> Just one question, why 50V? Just because it's very difficult to find 100nF ceramic capacitors
> of lower voltage, or 50V specification is truly needed (but why? it's a 3.3V circuit after all).

One of the problems with ceramic capacitors is the way they vary their capacitance with applied voltage. There is a good graph in the Microchip datasheets that discuss bypassing the Vcore voltage generated by internal voltage regulators that illustrates this. Essentially it becomes a case of using the highest rated voltage you can obtain in the case size you can fit gives the minimum change in capacitance with voltage.

This change in capacitance with voltage causes what audiophiles describe as 'capacitor distortion' in amplifiers.

50V used to be common, but as ceramics have improved and requirements for higher capacitance in smaller packages has forced the situation where lower voltages have become available.



--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
RussellMc
2017-12-04 00:23:06 UTC
Permalink
Errata and assorted stuff:

BAJ's


*​​Generally a canned oscillator will have a ground lead. So it's
notnecessary so add an additional one.*

is probably intended to be



*​​Generally a canned oscillator will have a ground lead. So it's
notnecessary ​TO add an additional one.*

*​______________*

*​*
I
​ have not yet read the cited tutorial, but note that with higher
oscillator frequencies "nowadays" and general process improvements, a well
sited 0.01 uF cap may be better than a 0.1 uF. If really keen, look at data
sheet response curves. At that stage you will also start looking at lead
lengths, track lenghts, inductances etc :-) - BUT 0.1 uF is usually fine.

50V is because that's what common or garden ones usually are.

​Jason mentions capacitance change with voltage and effect with
composition. ​
Add to that the affect of voltage steps on capacitor response. I've seen
accounts of capacitor ringing due to applies voltage step at power up
causing overvoltage transients which affected the "protected" IC. That is
probably more for larger capacitance reservoir caps. Probably.

The super cautious may also note possible microphonic affects where board
vibrations MAY modulate capacitance and possibly cause noise to be input
:-). Not usually an issue.

Not a capacitor, but, piezo sounders can produce voltages that will destroy
ICs when they are mechanically "modulated". I've seen accounts of systems
dying when a case is tapped due to this affect.



​ Russell​



On 3 December 2017 at 18:11, Electron <***@infinito.it> wrote:

>
> Thank you for all replies. I would like to address one in particular:
>
> Just one question, why 50V? Just because it's very difficult to find 100nF
> ceramic capacitors of lower voltage, or 50V specification is truly needed
> (but why? it's a 3.3V circuit after all).
>
> Thank you.
>
> Have a nice sunday,
> Mario
>
>
> At 00:15 2017-12-03, Richard Pope wrote:
> >Mario,
> > Yes! I won't go in to the reasons why. I bypass the Oscillator
> >and/or oscillators and all of the digital ICs. Linear VRs are also
> >bypassed but look at the datasheet to get the proper values. I mostly
> >use 0.1uF 50V Ceramics. I have at times used 0.01uF 50V Ceramics.
> >Thanks,
> >rich!
> >
> >On 12/2/2017 12:18 PM, Electron wrote:
> >> Hello,
> >> it may seem a banal question, but as it's the first time I use an
> external
> >> oscillator (with integrated crystal), I am not sure. The datasheet
> makes no
> >> mention whatsoever to the need to use a bypass capacitor in the power
> line:
> >>
> >> https://global.kyocera.com/prdct/electro/product/pdf/clock_k_e.pdf
> >>
> >> But is this truly the case?
> >>
> >> Should I put a (100nF?) bypass capacitor anyway in your opinion?
> >>
> >> Space on the board may be used for something else otherwise, so I don't
> >> want to put useless components. But then again who does.
> >>
> >> Also, I guess there's no advantage in grounding the metalcase on this
> >> integrated oscillator, like I use to do with Xtals. Maybe it's already
> >> grounded but I haven't received it yet.. I ask in case it's not.
> >>
> >> Thank you.
> >>
> >> Kind regards,
> >> Mario
> >>
> >
> >
> >---
> >This email has been checked for viruses by Avast antivirus software.
> >https://www.avast.com/antivirus
> >
> >--
> >http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> >View/change your membership options at
> >http://mailman.mit.edu/mailman/listinfo/piclist
>
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options a
Van Horn, David
2017-12-04 19:40:31 UTC
Permalink
Not a capacitor, but, piezo sounders can produce voltages that will destroy ICs when they are mechanically "modulated". I've seen accounts of systems dying when a case is tapped due to this affect.



​ Russell​


I once used an existing piezo beeper to generate a reset pulse if "smacked". It saved me adding a switch, and it actually worked well in the field.
Special case though. :)

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http:
Sean Breheny
2017-12-04 19:49:55 UTC
Permalink
One board I worked on >10 years ago (but I didn't witness this first-hand)
supposedly would reset if you played just the right frequency on the piezo
speaker. I don't recall whether the problem was overvoltage or something
else or exactly what was done to fix it.



On Mon, Dec 4, 2017 at 2:40 PM, Van Horn, David <
***@backcountryaccess.com> wrote:

>
> Not a capacitor, but, piezo sounders can produce voltages that will
> destroy ICs when they are mechanically "modulated". I've seen accounts of
> systems dying when a case is tapped due to this affect.
>
>
>
> ​ Russell​
>
>
> I once used an existing piezo beeper to generate a reset pulse if
> "smacked". It saved me adding a switch, and it actually worked well in
> the field.
> Special case though. :)
>
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/ma
Bob Blick
2017-12-04 20:20:02 UTC
Permalink
Try shining a strong light into a self-blinking LED - I have some RGB ones that freeze up if you do that.

Bob
________________________________________
From: piclist-***@mit.edu <piclist-***@mit.edu> on behalf of Sean Breheny
Sent: Monday, December 4, 2017 11:49 AM
To: Microcontroller discussion list - Public.
Subject: Re: [EE] Bypass capacitor really required?

One board I worked on >10 years ago (but I didn't witness this first-hand)
supposedly would reset if you played just the right frequency on the piezo
speaker. I don't recall whether the problem was overvoltage or something
else or exactly what was done to fix it.



On Mon, Dec 4, 2017 at 2:40 PM, Van Horn, David wrote:

>
> Not a capacitor, but, piezo sounders can produce voltages that will
> destroy ICs when they are mechanically "modulated". I've seen accounts of
> systems dying when a case is tapped due to this affect.
>
>
>
> ​ Russell​
>
>
> I once used an existing piezo beeper to generate a reset pulse if
> "smacked". It saved me adding a switch, and it actually worked well in
> the field.
> Special case though. :)
>

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mai
Sean Breheny
2017-12-04 20:26:42 UTC
Permalink
Ha! Do you think that this is caused by failure to shield the blinking IC
die from light or is it that the LED is acting as a photodiode and their
circuit isn't expecting that?

I have noticed before that neon lamps which are beginning to fail
(flickering) become sensitive to external bright light. Shining a bright
light on them will often make them stop flickering and stay on solid - I
think the light helps to make them ionize at a lower voltage.

On Mon, Dec 4, 2017 at 3:20 PM, Bob Blick <***@outlook.com> wrote:

> Try shining a strong light into a self-blinking LED - I have some RGB ones
> that freeze up if you do that.
>
> Bob
>
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
RussellMc
2017-12-06 04:44:32 UTC
Permalink
On 5 December 2017 at 09:20, Bob Blick <***@outlook.com> wrote:


> Try shining a strong light into a self-blinking LED - I have some RGB ones
> that freeze up if you do that.
>

​As opposed to circuits where shining a light on the lED powers the flasher
:-)

eg
http://www.shelbytvservice.com/schematics/led/self-powered%20LED.gif

I think I've seen one with less components that does not use an inductor.
Would be 'fun' to try


Russell

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership op
David C Brown
2017-12-04 19:52:19 UTC
Permalink
I bet you loved telling the customer. "Give it a kick and it will be
right" :-)

__________________________________________
David C Brown
43 Bings Road
Whaley Bridge
High Peak Phone: 01663 733236
Derbyshire eMail: ***@gmail.com
SK23 7ND web: www.bings-knowle.co.uk/dcb
<http://www.jb.man.ac.uk/~dcb>



*Sent from my etch-a-sketch*

On 4 December 2017 at 19:40, Van Horn, David <
***@backcountryaccess.com> wrote:

>
> Not a capacitor, but, piezo sounders can produce voltages that will
> destroy ICs when they are mechanically "modulated". I've seen accounts of
> systems dying when a case is tapped due to this affect.
>
>
>
> ​ Russell​
>
>
> I once used an existing piezo beeper to generate a reset pulse if
> "smacked". It saved me adding a switch, and it actually worked well in
> the field.
> Special case though. :)
>
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mi
s***@interlog.com
2017-12-04 19:56:06 UTC
Permalink
Quoting "Van Horn, David" <***@backcountryaccess.com>:

>
> Not a capacitor, but, piezo sounders can produce voltages that will
> destroy ICs when they are mechanically "modulated". I've seen
> accounts of systems dying when a case is tapped due to this affect.
>
>
>
> ​ Russell​
>
>
> I once used an existing piezo beeper to generate a reset pulse if
> "smacked". It saved me adding a switch, and it actually worked
> well in the field.
> Special case though. :)
>

Percussive software maintenance?



--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/pi
RussellMc
2017-12-04 00:11:18 UTC
Permalink
On 3 December 2017 at 12:15, Richard Pope <***@charter.net> wrote:


> Linear VRs are also
> bypassed but look at the datasheet to get the proper values.


​Yes. Reasonably well known but worth repeating.
The stability of many modern low dropout linear regulators is affected by
the ESR of the out[put capacitor. Often too high OR too low can cause
oscillation under some condition.s Which conditions may be custom selected
by Murphy.

Where this applies the datasheet (usually) specifies an acceptable ESR
range.


Russell​
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listi
Byron Jeff
2017-12-03 00:40:22 UTC
Permalink
Comments embedded inline...

On Sat, Dec 02, 2017 at 07:18:48PM +0100, Electron wrote:
>
> Hello,
> it may seem a banal question, but as it's the first time I use an external
> oscillator (with integrated crystal), I am not sure. The datasheet makes no
> mention whatsoever to the need to use a bypass capacitor in the power line:
>
> https://global.kyocera.com/prdct/electro/product/pdf/clock_k_e.pdf
>
> But is this truly the case?

Yes. The requirement is so prevalent that it's seldom explicitly mentions.

>
> Should I put a (100nF?) bypass capacitor anyway in your opinion?

Always. This tutorial discusses why it is needed, choosing appropriate
values, and different types of noise management and isolation:

http://www.thebox.myzen.co.uk/Tutorial/De-coupling.html

>
> Space on the board may be used for something else otherwise, so I don't
> want to put useless components. But then again who does.

Never useless.

>
> Also, I guess there's no advantage in grounding the metalcase on this
> integrated oscillator, like I use to do with Xtals. Maybe it's already
> grounded but I haven't received it yet.. I ask in case it's not.

Generally a canned oscillator will have a ground lead. So it's not
necessary so add an additional one.

> Thank you.
> Kind regards,
> Mario

No problem. Hope this helps,

BAJ
--
Byron A. Jeff
Associate Professor: Department of Computer Science and Information Technology
College of Information and Mathematical Sciences
Clayton State University
http://faculty.clayton.edu/bjeff
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
Sean Breheny
2017-12-03 02:47:56 UTC
Permalink
I like the decoupling tutorial page which Byron linked to. I also did a
little LT Spice simulation to illustrate the difference which decoupling
makes.

This simulation is based on the 74HC series output cell model given at the
end of this library:
https://www.classe.cornell.edu/~ib38/teaching/p360/lectures/wk12/l35/11.1/74hc.lib

The simulation is for a single 74HC series type output cell which is
roughly similar to what would be at the output of your oscillator. The
simulation has 100nH of inductance between the Vdd pin and true 3.3V, and
100nH between Vss and true GND. This represents about an inch of typical
PCB trace. The pulsed source inside is supposed to simulate the internal
oscillator circuit and is therefore referenced to the local internal Vss
net of the chip. I have given it a 15pF load which is the output load given
in the oscillator datasheet as typical. I show a 10MHz output. For many
cmos devices, the output stage dominates the pulsed load from the power
supply since it drives a much larger capacitance than internal nodes do.

Here's the simulation with only stray capacitance (10pF) as the bypass
capacitance:

https://s8.postimg.org/niw5n96at/Screenshot_from_2017-12-02_21_33_24.png

The green trace is the output waveform and the blue is the local Vdd-Vss
difference seen by the other internals of the chip. The ringing caused by
the pulsed supply current drawn from the rails interacting with the stray
inductance and capacitance is about 1.5V peak which could be enough to
cause glitches or other disturbances to the internal circuitry.

Here's the result with a 100nF bypass capacitor directly across Vdd, Vss:

https://s8.postimg.org/l1keg3had/Screenshot_from_2017-12-02_21_34_06.png

The ringing and ripple has almost disappeared from the power rails and the
output of the oscillator is cleaner, too.

Sean



On Sat, Dec 2, 2017 at 7:40 PM, Byron Jeff <***@clayton.edu> wrote:

> Comments embedded inline...
>
> On Sat, Dec 02, 2017 at 07:18:48PM +0100, Electron wrote:
> >
> > Hello,
> > it may seem a banal question, but as it's the first time I use an
> external
> > oscillator (with integrated crystal), I am not sure. The datasheet makes
> no
> > mention whatsoever to the need to use a bypass capacitor in the power
> line:
> >
> > https://global.kyocera.com/prdct/electro/product/pdf/clock_k_e.pdf
> >
> > But is this truly the case?
>
> Yes. The requirement is so prevalent that it's seldom explicitly mentions.
>
> >
> > Should I put a (100nF?) bypass capacitor anyway in your opinion?
>
> Always. This tutorial discusses why it is needed, choosing appropriate
> values, and different types of noise management and isolation:
>
> http://www.thebox.myzen.co.uk/Tutorial/De-coupling.html
>
> >
> > Space on the board may be used for something else otherwise, so I don't
> > want to put useless components. But then again who does.
>
> Never useless.
>
> >
> > Also, I guess there's no advantage in grounding the metalcase on this
> > integrated oscillator, like I use to do with Xtals. Maybe it's already
> > grounded but I haven't received it yet.. I ask in case it's not.
>
> Generally a canned oscillator will have a ground lead. So it's not
> necessary so add an additional one.
>
> > Thank you.
> > Kind regards,
> > Mario
>
> No problem. Hope this helps,
>
> BAJ
> --
> Byron A. Jeff
> Associate Professor: Department of Computer Science and Information
> Technology
> College of Information and Mathematical Sciences
> Clayton State University
> http://faculty.clayton.edu/bjeff
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
Electron
2017-12-03 05:15:03 UTC
Permalink
It doesn't get any better than this, as explanations can go. Thank you!

But nonetheless many thanks also to every other that replied.

Cheers,
Mario


At 03:47 2017-12-03, Sean Breheny wrote:
>I like the decoupling tutorial page which Byron linked to. I also did a
>little LT Spice simulation to illustrate the difference which decoupling
>makes.
>
>This simulation is based on the 74HC series output cell model given at the
>end of this library:
>https://www.classe.cornell.edu/~ib38/teaching/p360/lectures/wk12/l35/1
>1.1/74hc.lib
>
>The simulation is for a single 74HC series type output cell which is
>roughly similar to what would be at the output of your oscillator. The
>simulation has 100nH of inductance between the Vdd pin and true 3.3V, and
>100nH between Vss and true GND. This represents about an inch of typical
>PCB trace. The pulsed source inside is supposed to simulate the internal
>oscillator circuit and is therefore referenced to the local internal Vss
>net of the chip. I have given it a 15pF load which is the output load given
>in the oscillator datasheet as typical. I show a 10MHz output. For many
>cmos devices, the output stage dominates the pulsed load from the power
>supply since it drives a much larger capacitance than internal nodes do.
>
>Here's the simulation with only stray capacitance (10pF) as the bypass
>capacitance:
>
>https://s8.postimg.org/niw5n96at/Screenshot_from_2017-12-02_21_33_24.png
>
>The green trace is the output waveform and the blue is the local Vdd-Vss
>difference seen by the other internals of the chip. The ringing caused by
>the pulsed supply current drawn from the rails interacting with the stray
>inductance and capacitance is about 1.5V peak which could be enough to
>cause glitches or other disturbances to the internal circuitry.
>
>Here's the result with a 100nF bypass capacitor directly across Vdd, Vss:
>
>https://s8.postimg.org/l1keg3had/Screenshot_from_2017-12-02_21_34_06.png
>
>The ringing and ripple has almost disappeared from the power rails and the
>output of the oscillator is cleaner, too.
>
>Sean
>
>
>
>On Sat, Dec 2, 2017 at 7:40 PM, Byron Jeff <***@clayton.edu> wrote:
>
>> Comments embedded inline...
>>
>> On Sat, Dec 02, 2017 at 07:18:48PM +0100, Electron wrote:
>> >
>> > Hello,
>> > it may seem a banal question, but as it's the first time I use an
>> external
>> > oscillator (with integrated crystal), I am not sure. The datasheet makes
>> no
>> > mention whatsoever to the need to use a bypass capacitor in the power
>> line:
>> >
>> > https://global.kyocera.com/prdct/electro/product/pdf/clock_k_e.pdf
>> >
>> > But is this truly the case?
>>
>> Yes. The requirement is so prevalent that it's seldom explicitly mentions.
>>
>> >
>> > Should I put a (100nF?) bypass capacitor anyway in your opinion?
>>
>> Always. This tutorial discusses why it is needed, choosing appropriate
>> values, and different types of noise management and isolation:
>>
>> http://www.thebox.myzen.co.uk/Tutorial/De-coupling.html
>>
>> >
>> > Space on the board may be used for something else otherwise, so I don't
>> > want to put useless components. But then again who does.
>>
>> Never useless.
>>
>> >
>> > Also, I guess there's no advantage in grounding the metalcase on this
>> > integrated oscillator, like I use to do with Xtals. Maybe it's already
>> > grounded but I haven't received it yet.. I ask in case it's not.
>>
>> Generally a canned oscillator will have a ground lead. So it's not
>> necessary so add an additional one.
>>
>> > Thank you.
>> > Kind regards,
>> > Mario
>>
>> No problem. Hope this helps,
>>
>> BAJ
>> --
>> Byron A. Jeff
>> Associate Professor: Department of Computer Science and Information
>> Technology
>> College of Information and Mathematical Sciences
>> Clayton State University
>> http://faculty.clayton.edu/bjeff
>> --
>> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
>> View/change your membership options at
>> http://mailman.mit.edu/mailman/listinfo/piclist
>>
>--
>http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
>View/change your membership options at
>http://mailman.mit.edu/mailman/listinfo/piclist

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
Van Horn, David
2017-12-04 18:16:49 UTC
Permalink
Plenty of good answers, and I'll throw in a "HELL YES" as well.

I saw one instance of a product in production using an Atmel AVR, where there is a single pin which is an ADC AREF input only rather than a fully implemented I/O pin.
The application didn't use the ADC at all, and the designer thought he didn't need that bypass cap.
There was a box of boards which had failed production test, which had resisted all attempts to repair.
I added the specified bypass cap and recovered 100% of those boards.

If the data sheet specifies bypass caps, design them in. If it doesn't, design them in anyway, you can always DNP (do not populate) in production.

Bypasses are your friend. Route them well, and don't skimp. I use X2Y caps in critical applications. With any type of bypass cap I route so that power goes THROUGH the capacitor pad on its way to the chip, and the ground side of the cap returns directly to the nearest ground pin on the chip. Never a "tee" where the current has the option to go past the cap.

Similarly with crystal loading capacitors, where I route them directly to the nearest ground pin on the chip and nothing else touches that trace until it joins all the ground pours at the chip ground pin.
I have seen boards fail FCC testing hard because crystal caps were "grounded" into a 100 mil ground track that was about a quarter wavelength long at 400+ MHz. The "ground" actually worked more like a shunt fed antenna. :-P





--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
Sean Breheny
2017-12-04 19:32:16 UTC
Permalink
It's not the same as a purely digital example but I once designed a board
that used a direct digital synthesizer (DDS) to generate the reference for
a PLL in a microwave synthesizer. The measured phase noise of the DDS
output was significantly higher than it should have been, which resulted in
the final microwave output being pretty crappy since it was effectively
about 500x the DDS output frequency, so that both the bandwidth and the
magnitude of the noise sidebands were amplified. After scratching my head
for quite a while I came across a statement in the DDS datasheet which I
had not noticed before. There was a particular power pin which they said
should be bypassed TO a particular ground pin. I had bypassed that power
pin but the other side of the bypass cap just went to the GND plane and
that particular ground pin also went separately to the plane. I cut some
traces and tacked on a cap directly between those two pins and voila the
noise was cut by about 10dB in a wide swath of the noise bandwidth.

Another story to illustrate how much of a difference a rather short trace
or piece of wire can make. I've designed several moderate power (about 1kW)
motor drives. In one case, we were measuring current by placing one of
Allegro Microdevices' Hall-effect current sensors in line with the drains
of all three high-side FETs in a three-phase bridge. The sensor's current
sense path was a thick conductor only about 3cm long and specified to have
<100 microOhms resistance. The power plane that one end of the sensor
connected to was well bypassed with bulk capacitance close to the FETs, but
since we needed accurate current measurement on the timescale of a fraction
of a PWM cycle we couldn't bypass the FET drains - we had to allow all of
the supply current to flow through the sensor to the FETs. We ended up with
pretty large voltage spikes on the FET drains due to the inductance of the
sensor combined with the fast switching edges of the FET drain currents. We
anticipated this and had incorporated pads on the board for a snubber. I
computed the optimal snubber values and added them to the board. The
voltage spikes were much less but the snubber components were getting quite
warm! This turned out to be acceptable but it was amazing to see how a
relatively low frequency circuit (20kHz PWM) can be affected by only a few
nanoHenries of inductance and can in fact transfer almost 1% of its power
through the energy stored in that tiny inductance each PWM cycle. Of
course, this is because this circuit had very fast (about 100ns) current
rise and fall times as the FETs switched on and off and the resulting dI/dt
was large enough to produce several volts across just a few nH.



On Mon, Dec 4, 2017 at 1:16 PM, Van Horn, David <
***@backcountryaccess.com> wrote:

> Plenty of good answers, and I'll throw in a "HELL YES" as well.
>
> I saw one instance of a product in production using an Atmel AVR, where
> there is a single pin which is an ADC AREF input only rather than a fully
> implemented I/O pin.
> The application didn't use the ADC at all, and the designer thought he
> didn't need that bypass cap.
> There was a box of boards which had failed production test, which had
> resisted all attempts to repair.
> I added the specified bypass cap and recovered 100% of those boards.
>
> If the data sheet specifies bypass caps, design them in. If it doesn't,
> design them in anyway, you can always DNP (do not populate) in production.
>
> Bypasses are your friend. Route them well, and don't skimp. I use X2Y
> caps in critical applications. With any type of bypass cap I route so that
> power goes THROUGH the capacitor pad on its way to the chip, and the ground
> side of the cap returns directly to the nearest ground pin on the chip.
> Never a "tee" where the current has the option to go past the cap.
>
> Similarly with crystal loading capacitors, where I route them directly to
> the nearest ground pin on the chip and nothing else touches that trace
> until it joins all the ground pours at the chip ground pin.
> I have seen boards fail FCC testing hard because crystal caps were
> "grounded" into a 100 mil ground track that was about a quarter wavelength
> long at 400+ MHz. The "ground" actually worked more like a shunt fed
> antenna. :-P
>
>
>
>
>
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
a***@stfc.ac.uk
2017-12-04 23:51:24 UTC
Permalink
> It's not the same as a purely digital example but I once designed a board that used a direct
> digital synthesizer (DDS) to generate the reference for a PLL in a microwave synthesizer.
...
>
>> I saw one instance of a product in production using an Atmel AVR,
>> where there is a single pin which is an ADC AREF input only rather
>> than a fully implemented I/O pin.
...

These two stories remind me of a story that appeared in Electronics Australia "Serviceman who tells" feature. This was a column written by someone whose identity was concealed by the editor, but ran a typical one man radio/TV service business in a suburb of Sydney, Australia. This particular story was related to him by another serviceman who ran a similar business in an area that had a number of residential tower blocks in his 'catchment area'. This particular story concerned a customer whose TV would periodically not receive a certain TV channel, even though they were line of site to the transmitter. Said customer was some way up one of the tower blocks, and despite some visits to the abode the problem was not diagnosed. Eventually customer was told to call him immediately the problem recurred and he would come around promptly. In due time said phone call happened, so serviceman goes to the home and sure enough the channel concerned was just visible in the snow that was typ!
ical of a very weak signal in the days of analogue TV. No matter what he did to the set to attempt to repair the problem produced any improvement, so after some time he ends up standing in customers lounge pondering what the cause of this strange loss of channel was - it was one specific channel, all the other channels were as strong a signal as they had ever had. His eyes are wandering around the apartment as he was thinking, and he realised that son was playing with his train set on the floor - and the loop of track was about right size for a dipole at the VHF frequency of the channel concerned. A moments stoppage of the train and breaking a track joint soon restored the picture on the channel of interest.

Another story from the same source concerned a colour TV that would give only B&W pictures on a certain channel. This was eventually tracked down to the 300 ohm ribbon from the terminals on the back of the cabinet to the tuner being secured with a piece of wire looped around a suitable point and then had the ends twisted to secure the ribbon cable conveniently out of the way. The loop combined with the twisted ends combined to make a tuned circuit at the colour burst carrier frequency on this particular channel which acted as a trap preventing the colour burst from reaching the tuner. A quick trim of the amount of twisted portion (which were fairly long) produced colour pictures.

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
s***@agilent.com
2017-12-05 01:01:15 UTC
Permalink
Ahh - The glory days of EA and the Serviceman...

My favourite story was of the time "he" was called to fix an old mantle radio - a cabinet AM model with valves. He pulled it away from the wall to find a shrivelled, mouldy sausage pushed in behind. "That's right" said The Owner. "I remember - if you touch that wire the reception was much better so we stuck the sausage there."

Apocryphal and one I have heard elsewhere but first read in the Serviceman about 1969...

That reminds me - I was in my local electronics hobbyist store recently and spotted <https://diyodemag.com/> a new electronics print magazine. Rare to see in this digital era! The usual Arduino/Raspi projects expected these days but also a smattering theory (Bresenham and transistors in the current issue). Online as well of course but PRINT! I wish them success!

Stephen


-----Original Message-----
From: piclist-***@mit.edu [mailto:piclist-***@mit.edu] On Behalf Of ***@stfc.ac.uk
Sent: Tuesday, 5 December 2017 10:51 AM
To: ***@mit.edu
Subject: RE: [EE] Bypass capacitor really required?

> It's not the same as a purely digital example but I once designed a
> board that used a direct digital synthesizer (DDS) to generate the reference for a PLL in a microwave synthesizer.
...
>
>> I saw one instance of a product in production using an Atmel AVR,
>> where there is a single pin which is an ADC AREF input only rather
>> than a fully implemented I/O pin.
...

These two stories remind me of a story that appeared in Electronics Australia "Serviceman who tells" feature. This was a column written by someone whose identity was concealed by the editor, but ran a typical one man radio/TV service business in a suburb of Sydney, Australia. This particular story was related to him by another serviceman who ran a similar business in an area that had a number of residential tower blocks in his 'catchment area'. This particular story concerned a customer whose TV would periodically not receive a certain TV channel, even though they were line of site to the transmitter. Said customer was some way up one of the tower blocks, and despite some visits to the abode the problem was not diagnosed. Eventually customer was told to call him immediately the problem recurred and he would come around promptly. In due time said phone call happened, so serviceman goes to the home and sure enough the channel concerned was just visible in the snow that was typ!
ical of a very weak signal in the days of analogue TV. No matter what he did to the set to attempt to repair the problem produced any improvement, so after some time he ends up standing in customers lounge pondering what the cause of this strange loss of channel was - it was one specific channel, all the other channels were as strong a signal as they had ever had. His eyes are wandering around the apartment as he was thinking, and he realised that son was playing with his train set on the floor - and the loop of track was about right size for a dipole at the VHF frequency of the channel concerned. A moments stoppage of the train and breaking a track joint soon restored the picture on the channel of interest.

Another story from the same source concerned a colour TV that would give only B&W pictures on a certain channel. This was eventually tracked down to the 300 ohm ribbon from the terminals on the back of the cabinet to the tuner being secured with a piece of wire looped around a suitable point and then had the ends twisted to secure the ribbon cable conveniently out of the way. The loop combined with the twisted ends combined to make a tuned circuit at the colour burst carrier frequency on this particular channel which acted as a trap preventing the colour burst from reaching the tuner. A quick trim of the amount of twisted portion (which were fairly long) produced colour pictures.

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
a***@stfc.ac.uk
2017-12-05 09:43:40 UTC
Permalink
> Ahh - The glory days of EA and the Serviceman...

Yes, I was an avid reader of the stories ...

>
> My favourite story was of the time "he" was called to fix an old mantle radio -
> a cabinet AM model with valves. He pulled it away from the wall to find a
> shrivelled, mouldy sausage pushed in behind. "That's right" said The Owner.
> "I remember - if you touch that wire the reception was much better so we
> stuck the sausage there."
>
> Apocryphal and one I have heard elsewhere but first read in the Serviceman
> about 1969...

I remember that one too. IIRC it was on an outback station, and they didn't have a proper aerial.



--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
s***@agilent.com
2017-12-06 00:22:46 UTC
Permalink
Yep - that was the one ;o)
Now - just bin it :o(

S.


-----Original Message-----
From: piclist-***@mit.edu [mailto:piclist-***@mit.edu] On Behalf Of ***@stfc.ac.uk
Sent: Tuesday, 5 December 2017 8:44 PM
To: ***@mit.edu
Subject: RE: [EE] Bypass capacitor really required?

> Ahh - The glory days of EA and the Serviceman...

Yes, I was an avid reader of the stories ...

>
> My favourite story was of the time "he" was called to fix an old
> mantle radio - a cabinet AM model with valves. He pulled it away from
> the wall to find a shrivelled, mouldy sausage pushed in behind. "That's right" said The Owner.
> "I remember - if you touch that wire the reception was much better so
> we stuck the sausage there."
>
> Apocryphal and one I have heard elsewhere but first read in the
> Serviceman about 1969...

I remember that one too. IIRC it was on an outback station, and they didn't have a proper aerial.



--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
Sean Breheny
2017-12-05 05:40:09 UTC
Permalink
Thanks, Alan, those are pretty good stories :)


On Mon, Dec 4, 2017 at 6:51 PM, <***@stfc.ac.uk> wrote:

>
> These two stories remind me of a story that appeared in Electronics
> Australia "Serviceman who tells" feature. This was a column written by
> someone whose identity was concealed by the editor, but ran a typical one
> man radio/TV service business in a suburb of Sydney, Australia. This
> particular story was related to him by another serviceman who ran a similar
> business in an area that had a number of residential tower blocks in his
> 'catchment area'. This particular story concerned a customer whose TV would
> periodically not receive a certain TV channel, even though they were line
> of site to the transmitter. Said customer was some way up one of the tower
> blocks, and despite some visits to the abode the problem was not diagnosed.
> Eventually customer was told to call him immediately the problem recurred
> and he would come around promptly. In due time said phone call happened, so
> serviceman goes to the home and sure enough the channel concerned was just
> visible in the snow that was typ!
> ical of a very weak signal in the days of analogue TV. No matter what he
> did to the set to attempt to repair the problem produced any improvement,
> so after some time he ends up standing in customers lounge pondering what
> the cause of this strange loss of channel was - it was one specific
> channel, all the other channels were as strong a signal as they had ever
> had. His eyes are wandering around the apartment as he was thinking, and he
> realised that son was playing with his train set on the floor - and the
> loop of track was about right size for a dipole at the VHF frequency of the
> channel concerned. A moments stoppage of the train and breaking a track
> joint soon restored the picture on the channel of interest.
>
> Another story from the same source concerned a colour TV that would give
> only B&W pictures on a certain channel. This was eventually tracked down to
> the 300 ohm ribbon from the terminals on the back of the cabinet to the
> tuner being secured with a piece of wire looped around a suitable point and
> then had the ends twisted to secure the ribbon cable conveniently out of
> the way. The loop combined with the twisted ends combined to make a tuned
> circuit at the colour burst carrier frequency on this particular channel
> which acted as a trap preventing the colour burst from reaching the tuner.
> A quick trim of the amount of twisted portion (which were fairly long)
> produced colour pictures.
>
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
a***@stfc.ac.uk
2017-12-05 09:45:46 UTC
Permalink
> Thanks, Alan, those are pretty good stories :)

You're welcome, it just reminds one of the 'fickleness' and 'literal dealings' of RF interacting with things you don't appreciate and think wouldn't matter.



--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
Clint Jay
2017-12-05 10:28:37 UTC
Permalink
Ah Les Lawry Johns column in Television mag, an acute observation of the
human condition, there was also tales of the aerial rigger which shed light
on some of the less pleasant people us telly engineers encountered

On 5 Dec 2017 09:45, <***@stfc.ac.uk> wrote:

> > Thanks, Alan, those are pretty good stories :)
>
> You're welcome, it just reminds one of the 'fickleness' and 'literal
> dealings' of RF interacting with things you don't appreciate and think
> wouldn't matter.
>
>
>
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
Ryan O'Connor
2017-12-04 20:48:00 UTC
Permalink
I have a question about this... is there really a difference between "route
so that power goes THROUGH the capacitor pad on its way to the chip" and
not? Does anyone have empirical evidence of this working vs not? Or is it
just something people have imagined?

Just curious as have not seen any tests around which prove the need for it.

Ryan




On 5 December 2017 at 07:16, Van Horn, David <
***@backcountryaccess.com> wrote:

> Plenty of good answers, and I'll throw in a "HELL YES" as well.
>
> I saw one instance of a product in production using an Atmel AVR, where
> there is a single pin which is an ADC AREF input only rather than a fully
> implemented I/O pin.
> The application didn't use the ADC at all, and the designer thought he
> didn't need that bypass cap.
> There was a box of boards which had failed production test, which had
> resisted all attempts to repair.
> I added the specified bypass cap and recovered 100% of those boards.
>
> If the data sheet specifies bypass caps, design them in. If it doesn't,
> design them in anyway, you can always DNP (do not populate) in production.
>
> Bypasses are your friend. Route them well, and don't skimp. I use X2Y
> caps in critical applications. With any type of bypass cap I route so that
> power goes THROUGH the capacitor pad on its way to the chip, and the ground
> side of the cap returns directly to the nearest ground pin on the chip.
> Never a "tee" where the current has the option to go past the cap.
>
> Similarly with crystal loading capacitors, where I route them directly to
> the nearest ground pin on the chip and nothing else touches that trace
> until it joins all the ground pours at the chip ground pin.
> I have seen boards fail FCC testing hard because crystal caps were
> "grounded" into a 100 mil ground track that was about a quarter wavelength
> long at 400+ MHz. The "ground" actually worked more like a shunt fed
> antenna. :-P
>
>
>
>
>
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
Van Horn, David
2017-12-04 21:04:29 UTC
Permalink
The Tee connection would add series inductance, in addition to that of the cap itself, lowering the self resonant frequency. The better the cap and ground system, the more difference the routing makes. Johanson X2Y caps are pretty good caps.

I did an SMPS design years ago where I saw a 2dB reduction in EMI by routing the track from the output diode to the capacitor lead (thruhole cap) to the output rather than routing those three points as a small flood, which allowed current to take either path.
I usually do very well on radiated emissions, in the "are you sure it's on" domain rather than "well, it's probably going to pass", by using the tracks I must have to work for me rather than against me.


-----Original Message-----
From: piclist-***@mit.edu [mailto:piclist-***@mit.edu] On Behalf Of Ryan O'Connor
Sent: Monday, December 4, 2017 1:48 PM
To: Microcontroller discussion list - Public.
Subject: Re: [EE] Bypass capacitor really required?

I have a question about this... is there really a difference between "route so that power goes THROUGH the capacitor pad on its way to the chip" and not? Does anyone have empirical evidence of this working vs not? Or is it just something people have imagined?

Just curious as have not seen any tests around which prove the need for it.

Ryan




On 5 December 2017 at 07:16, Van Horn, David < ***@backcountryaccess.com> wrote:

> Plenty of good answers, and I'll throw in a "HELL YES" as well.
>
> I saw one instance of a product in production using an Atmel AVR,
> where there is a single pin which is an ADC AREF input only rather
> than a fully implemented I/O pin.
> The application didn't use the ADC at all, and the designer thought he
> didn't need that bypass cap.
> There was a box of boards which had failed production test, which had
> resisted all attempts to repair.
> I added the specified bypass cap and recovered 100% of those boards.
>
> If the data sheet specifies bypass caps, design them in. If it
> doesn't, design them in anyway, you can always DNP (do not populate) in production.
>
> Bypasses are your friend. Route them well, and don't skimp. I use X2Y
> caps in critical applications. With any type of bypass cap I route so
> that power goes THROUGH the capacitor pad on its way to the chip, and
> the ground side of the cap returns directly to the nearest ground pin on the chip.
> Never a "tee" where the current has the option to go past the cap.
>
> Similarly with crystal loading capacitors, where I route them directly
> to the nearest ground pin on the chip and nothing else touches that
> trace until it joins all the ground pours at the chip ground pin.
> I have seen boards fail FCC testing hard because crystal caps were
> "grounded" into a 100 mil ground track that was about a quarter
> wavelength long at 400+ MHz. The "ground" actually worked more like a
> shunt fed antenna. :-P
>
>
>
>
>
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
Sean Breheny
2017-12-04 21:30:25 UTC
Permalink
I do use this technique but I have not done actual testing to determine how
much difference it makes. However, on paper it looks beneficial.

Bear in mind that we are really talking about two different reasons for
bypassing here: circuit reliability and EMC (electromagnetic compliance).
David's technique is really mostly about the EMC part. Depending on the
exact circumstances his technique may help or slightly hurt the circuit
reliability part. It can almost always be done in a way which doesn't
negatively impact circuit performance.

David's technique is about minimizing the amount of high frequency current
flowing in paths which are long enough to have significant radiation
resistance (i.e. "make good antennas"). Such a path need not be in a trace
- it could even be in a plane.

The circuit performance aspect focusses on minimizing the impedance (and
the Q factor) of the power and GND nodes as seen by the chip, so that
supply current pulses do not cause droop or "ground bounce".

Sean


On Mon, Dec 4, 2017 at 3:48 PM, Ryan O'Connor <***@gmail.com> wrote:

> I have a question about this... is there really a difference between "route
> so that power goes THROUGH the capacitor pad on its way to the chip" and
> not? Does anyone have empirical evidence of this working vs not? Or is it
> just something people have imagined?
>
> Just curious as have not seen any tests around which prove the need for it.
>
> Ryan
>
>
>
>
> On 5 December 2017 at 07:16, Van Horn, David <
> ***@backcountryaccess.com> wrote:
>
> > Plenty of good answers, and I'll throw in a "HELL YES" as well.
> >
> > I saw one instance of a product in production using an Atmel AVR, where
> > there is a single pin which is an ADC AREF input only rather than a fully
> > implemented I/O pin.
> > The application didn't use the ADC at all, and the designer thought he
> > didn't need that bypass cap.
> > There was a box of boards which had failed production test, which had
> > resisted all attempts to repair.
> > I added the specified bypass cap and recovered 100% of those boards.
> >
> > If the data sheet specifies bypass caps, design them in. If it doesn't,
> > design them in anyway, you can always DNP (do not populate) in
> production.
> >
> > Bypasses are your friend. Route them well, and don't skimp. I use X2Y
> > caps in critical applications. With any type of bypass cap I route so
> that
> > power goes THROUGH the capacitor pad on its way to the chip, and the
> ground
> > side of the cap returns directly to the nearest ground pin on the chip.
> > Never a "tee" where the current has the option to go past the cap.
> >
> > Similarly with crystal loading capacitors, where I route them directly to
> > the nearest ground pin on the chip and nothing else touches that trace
> > until it joins all the ground pours at the chip ground pin.
> > I have seen boards fail FCC testing hard because crystal caps were
> > "grounded" into a 100 mil ground track that was about a quarter
> wavelength
> > long at 400+ MHz. The "ground" actually worked more like a shunt fed
> > antenna. :-P
> >
> >
> >
> >
> >
> > --
> > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> > View/change your membership options at
> > http://mailman.mit.edu/mailman/listinfo/piclist
> >
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
Van Horn, David
2017-12-04 21:58:29 UTC
Permalink
Agreed, but they aren't actually separate items. More of a case of degree.
When you have to pass RF susceptibility testing and ESD testing and fast transient testing as well as emissions very good bypassing is probably the least expensive way to get there.
I've had bare two layer circuit boards pass susceptibility testing at 192V/m (the measuring equipment couldn't stand more, my board was fine)
I've not had issues with ESD or fast transient testing.

I'm an absolute sadist with testing, it has served me well for a long time.
ESD testing can be done with the Schaffner gun, but this is a lot more fun: http://sciedwiki.pppl.wikispaces.net/ETP+High+Frequency+Generator
50kV at 3-4A, risetime about 30nS.



-----Original Message-----
From: piclist-***@mit.edu [mailto:piclist-***@mit.edu] On Behalf Of Sean Breheny
Sent: Monday, December 4, 2017 2:30 PM
To: Microcontroller discussion list - Public.
Subject: Re: [EE] Bypass capacitor really required?

I do use this technique but I have not done actual testing to determine how much difference it makes. However, on paper it looks beneficial.

Bear in mind that we are really talking about two different reasons for bypassing here: circuit reliability and EMC (electromagnetic compliance).
David's technique is really mostly about the EMC part. Depending on the exact circumstances his technique may help or slightly hurt the circuit reliability part. It can almost always be done in a way which doesn't negatively impact circuit performance.

David's technique is about minimizing the amount of high frequency current flowing in paths which are long enough to have significant radiation resistance (i.e. "make good antennas"). Such a path need not be in a trace
- it could even be in a plane.

The circuit performance aspect focusses on minimizing the impedance (and the Q factor) of the power and GND nodes as seen by the chip, so that supply current pulses do not cause droop or "ground bounce".

Sean


On Mon, Dec 4, 2017 at 3:48 PM, Ryan O'Connor <***@gmail.com> wrote:

> I have a question about this... is there really a difference between
> "route so that power goes THROUGH the capacitor pad on its way to the
> chip" and not? Does anyone have empirical evidence of this working vs
> not? Or is it just something people have imagined?
>
> Just curious as have not seen any tests around which prove the need for it.
>
> Ryan
>
>
>
>
> On 5 December 2017 at 07:16, Van Horn, David <
> ***@backcountryaccess.com> wrote:
>
> > Plenty of good answers, and I'll throw in a "HELL YES" as well.
> >
> > I saw one instance of a product in production using an Atmel AVR,
> > where there is a single pin which is an ADC AREF input only rather
> > than a fully implemented I/O pin.
> > The application didn't use the ADC at all, and the designer thought
> > he didn't need that bypass cap.
> > There was a box of boards which had failed production test, which
> > had resisted all attempts to repair.
> > I added the specified bypass cap and recovered 100% of those boards.
> >
> > If the data sheet specifies bypass caps, design them in. If it
> > doesn't, design them in anyway, you can always DNP (do not populate)
> > in
> production.
> >
> > Bypasses are your friend. Route them well, and don't skimp. I use X2Y
> > caps in critical applications. With any type of bypass cap I route
> > so
> that
> > power goes THROUGH the capacitor pad on its way to the chip, and the
> ground
> > side of the cap returns directly to the nearest ground pin on the chip.
> > Never a "tee" where the current has the option to go past the cap.
> >
> > Similarly with crystal loading capacitors, where I route them
> > directly to the nearest ground pin on the chip and nothing else
> > touches that trace until it joins all the ground pours at the chip ground pin.
> > I have seen boards fail FCC testing hard because crystal caps were
> > "grounded" into a 100 mil ground track that was about a quarter
> wavelength
> > long at 400+ MHz. The "ground" actually worked more like a shunt
> > fed antenna. :-P
> >
> >
> >
> >
> >
> > --
> > http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> > View/change your membership options at
> > http://mailman.mit.edu/mailman/listinfo/piclist
> >
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
a***@stfc.ac.uk
2017-12-04 23:26:51 UTC
Permalink
There are four terminal capacitors made for SMPS units for exactly this reason - to ensure that lead inductance doesn't affect the bypassing done by the cap.


-----Original Message-----
From: piclist-***@mit.edu [mailto:piclist-***@mit.edu] On Behalf Of Ryan O'Connor
Sent: 04 December 2017 20:48
To: Microcontroller discussion list - Public. <***@mit.edu>
Subject: Re: [EE] Bypass capacitor really required?

I have a question about this... is there really a difference between "route so that power goes THROUGH the capacitor pad on its way to the chip" and not? Does anyone have empirical evidence of this working vs not? Or is it just something people have imagined?

Just curious as have not seen any tests around which prove the need for it.

Ryan




On 5 December 2017 at 07:16, Van Horn, David < ***@backcountryaccess.com> wrote:

> Plenty of good answers, and I'll throw in a "HELL YES" as well.
>
> I saw one instance of a product in production using an Atmel AVR,
> where there is a single pin which is an ADC AREF input only rather
> than a fully implemented I/O pin.
> The application didn't use the ADC at all, and the designer thought he
> didn't need that bypass cap.
> There was a box of boards which had failed production test, which had
> resisted all attempts to repair.
> I added the specified bypass cap and recovered 100% of those boards.
>
> If the data sheet specifies bypass caps, design them in. If it
> doesn't, design them in anyway, you can always DNP (do not populate) in production.
>
> Bypasses are your friend. Route them well, and don't skimp. I use X2Y
> caps in critical applications. With any type of bypass cap I route so
> that power goes THROUGH the capacitor pad on its way to the chip, and
> the ground side of the cap returns directly to the nearest ground pin on the chip.
> Never a "tee" where the current has the option to go past the cap.
>
> Similarly with crystal loading capacitors, where I route them directly
> to the nearest ground pin on the chip and nothing else touches that
> trace until it joins all the ground pours at the chip ground pin.
> I have seen boards fail FCC testing hard because crystal caps were
> "grounded" into a 100 mil ground track that was about a quarter
> wavelength long at 400+ MHz. The "ground" actually worked more like a
> shunt fed antenna. :-P
>
>
>
>
>
> --
> http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
> View/change your membership options at
> http://mailman.mit.edu/mailman/listinfo/piclist
>
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist

--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
Anthony Nixon
2017-12-05 05:29:52 UTC
Permalink
The PIC18F47K40 data sheet recommends this approach for both sets of power pins.

cheers

Tony

On Tue, Dec 5, 2017 at 7:48 AM, Ryan O'Connor <***@gmail.com> wrote:
> I have a question about this... is there really a difference between "route
> so that power goes THROUGH the capacitor pad on its way to the chip" and
> not? Does anyone have empirical evidence of this working vs not? Or is it
> just something people have imagined?
>
> Just curious as have not seen any tests around which prove the need for it.
>
> Ryan
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
Loading...