[PIC] I2C slave mode confusion

[Neil]

Trying to write a robust I2C slave routine for a PIC18F24Q10, but having
some "challenges". Current challenges...

- On page 443 of the datasheet (
http://ww1.microchip.com/downloads/en/DeviceDoc/PIC18F24-25Q10-Data-Sheet-DS40001945B.pdf
),
section 26.5.2 says that with SEN bit set in SSPxCON2, the clock will
stretch until the CKP bit is cleared.
Section 26.5.6.1 also mentions the SEN bit will automatically stretch
the clock after ACK/NAK.
However, the SSPxCON2 register definition says that the SEN bit is only
for master mode.  Huh?

- Section 26.5.2.1 is for 7-bit reception (implicitly with AHEN and
DHEN, because that's the section below.
In step 4 that SSPxIF flag is set.
Then in step 5, it says the SSPxIF flag is cleared (by the firmware),
and after that SSPxBUF is read.
Why is this?  If clock stretching is enabled, can't I read SSPxBUF, do
what I want (including streaming some debug data out the serial port),
then set CKP and then release SSPxIF?

- Section 26.4.10 says that "The 26.9.4.3 SCIE and 26.9.4.2 PCIE bits
can enable the generation of an interrupt in Slave modes that do not
typically support this function."
I take this to mean that in some modes, start and stop conditions will
generate interrupts.  In other modes, start and stop condition
interrupts can be enabled by setting these bits.
Can I not get interrupts on start and stop condition?

Cheers,
-Neil.