[EE] minimizing capacitance between tracks

[Van Horn, David]

A fun thought:

I have a PCB with six layers. I am looking for ways to minimize capacitive coupling between tracks on the top and tracks on the bottom.

If I think of the tracks as parallel plates, and the PCB as the dielectric, then that gives me a certain C, a bit bigger than suggested by the directly overlapping area.

Now what happens if I put a small copper dot, floating, in layer 3 or 4? It seems like this should create a series pair of capacitors of about twice the value, and no net change, but I keep thinking that the end result has to be a little less C than the first case.

Is there something freeware-ish that I can use to model a three (or more) plate capacitor where the middle plates are floating?


--
David VanHorn
Lead Hardware Engineer

Backcountry Access, Inc.
2820 Wilderness Pl, Unit H
Boulder, CO 80301 USA
phone: [phone] x110
email: ***@backcountryaccess.com<mailto:***@backcountryaccess.com>

[l***@gmail.com]

David,The floating layer is like two capacitors electrodes connected in series. So now you get two larger capacitors in series instead of a single one.
My $0.02Jean-Paul N1JPL 

Sent from Yahoo Mail on Android

On Mon, Mar 19, 2018 at 12:51 PM, Van Horn, David<***@backcountryaccess.com> wrote:
A fun thought:

I have a PCB with six layers.  I am looking for ways to minimize capacitive coupling between tracks on the top and tracks on the bottom.

If I think of the tracks as parallel plates, and the PCB as the dielectric, then that gives me a certain C, a bit bigger than suggested by the directly overlapping area.

Now what happens if I put a small copper dot, floating, in layer 3 or 4?  It seems like this should create a series pair of capacitors of about twice the value, and no net change, but I keep thinking that the end result has to be a little less C than the first case.

Is there something freeware-ish that I can use to model a three (or more) plate capacitor where the middle plates are floating?


--
David VanHorn
Lead Hardware Engineer

Backcountry Access, Inc.
2820 Wilderness Pl, Unit H
Boulder, CO  80301 USA
phone: [phone]  x110
email: ***@backcountryaccess.com<mailto:***@backcountryaccess.com>

[Van Horn, David]

Right. If I assume the middle plate is equidistant (probably not true in real life) then we get 2C in series with 2C for the same value.
However, there are fringing effects at the edges of all the plates, and that creates some additional C.
Something’s nagging at me that there’s a way to reduce the total C between the outer plates.

I also have the option of using a grid of dots as the middle “plate”.


From: ***@gmail.com <***@gmail.com>
Sent: Monday, March 19, 2018 11:07 AM
To: Microcontroller discussion list - Public. <***@mit.edu>; Van Horn, David <***@backcountryaccess.com>; Microcontroller discussion list - Public. <***@mit.edu>
Subject: Re: [EE] minimizing capacitance between tracks

David,
The floating layer is like two capacitors electrodes connected in series. So now you get two larger capacitors in series instead of a single one.

My $0.02
Jean-Paul
N1JPL
Sent from Yahoo Mail on Android<https://overview.mail.yahoo.com/mobile/?.src=Android>

On Mon, Mar 19, 2018 at 12:51 PM, Van Horn, David
<***@backcountryaccess.com<mailto:***@backcountryaccess.com>> wrote:

A fun thought:

I have a PCB with six layers. I am looking for ways to minimize capacitive coupling between tracks on the top and tracks on the bottom.

If I think of the tracks as parallel plates, and the PCB as the dielectric, then that gives me a certain C, a bit bigger than suggested by the directly overlapping area.

Now what happens if I put a small copper dot, floating, in layer 3 or 4? It seems like this should create a series pair of capacitors of about twice the value, and no net change, but I keep thinking that the end result has to be a little less C than the first case.

Is there something freeware-ish that I can use to model a three (or more) plate capacitor where the middle plates are floating?
--
David VanHorn
Lead Hardware Engineer

Backcountry Access, Inc.
2820 Wilderness Pl, Unit H
Boulder, CO 80301 USA
phone: [phone] x110
email: ***@backcountryaccess.com<mailto:***@backcountryaccess.com><mailto:***@backcountryaccess.com<mailto:***@backcountryaccess.com>>

[a***@stfc.ac.uk]

Somethings nagging ???

How about connecting the inner tracks to ground, that will cut the crosstalk between the outer layers.


-----Original Message-----
From: piclist-***@mit.edu [mailto:piclist-***@mit.edu] On Behalf Of Van Horn, David
Sent: 19 March 2018 17:11
To: ***@gmail.com; Microcontroller discussion list - Public. <***@mit.edu>
Subject: RE: [EE] minimizing capacitance between tracks

Right. If I assume the middle plate is equidistant (probably not true in real life) then we get 2C in series with 2C for the same value.
However, there are fringing effects at the edges of all the plates, and that creates some additional C.
Something’s nagging at me that there’s a way to reduce the total C between the outer plates.

I also have the option of using a grid of dots as the middle “plate”.


From: ***@gmail.com <***@gmail.com>
Sent: Monday, March 19, 2018 11:07 AM
To: Microcontroller discussion list - Public. <***@mit.edu>; Van Horn, David <***@backcountryaccess.com>; Microcontroller discussion list - Public. <***@mit.edu>
Subject: Re: [EE] minimizing capacitance between tracks

David,
The floating layer is like two capacitors electrodes connected in series. So now you get two larger capacitors in series instead of a single one.

My $0.02
Jean-Paul
N1JPL
Sent from Yahoo Mail on Android<https://overview.mail.yahoo.com/mobile/?.src=Android>

On Mon, Mar 19, 2018 at 12:51 PM, Van Horn, David <***@backcountryaccess.com<mailto:***@backcountryaccess.com>> wrote:

A fun thought:

I have a PCB with six layers. I am looking for ways to minimize capacitive coupling between tracks on the top and tracks on the bottom.

If I think of the tracks as parallel plates, and the PCB as the dielectric, then that gives me a certain C, a bit bigger than suggested by the directly overlapping area.

Now what happens if I put a small copper dot, floating, in layer 3 or 4? It seems like this should create a series pair of capacitors of about twice the value, and no net change, but I keep thinking that the end result has to be a little less C than the first case.

Is there something freeware-ish that I can use to model a three (or more) plate capacitor where the middle plates are floating?


--
David VanHorn
Lead Hardware Engineer

Backcountry Access, Inc.
2820 Wilderness Pl, Unit H
Boulder, CO 80301 USA
phone: [phone] x110
email: ***@backcountryaccess.com<mailto:***@backcountryaccess.com><mailto:***@backcountryaccess.com<mailto:***@backcountryaccess.com>>

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[Van Horn, David]

I'm trying to reduce trace capacitance here. I have plenty of ground nearby, but that would shoot up the parasitics.

I can't help thinking though, that I could plant a dot on an inner layer where LY1 and LY6 cross, and it seems like the total C should go down at least a little. The dot might have to be impractically small..

I'm just looking for any more tricks I can pull to shrink the parasitics.

The tracks are already minimum width. I haven't tried adjusting the pad geometries. Pulling back on ground in the immediate area helps.
Maybe there's nothing else practical.



-----Original Message-----
From: piclist-***@mit.edu <piclist-***@mit.edu> On Behalf Of ***@stfc.ac.uk
Sent: Monday, March 19, 2018 5:08 PM
To: ***@mit.edu
Subject: RE: [EE] minimizing capacitance between tracks

Somethings nagging ???

How about connecting the inner tracks to ground, that will cut the crosstalk between the outer layers.


-----Original Message-----
From: piclist-***@mit.edu [mailto:piclist-***@mit.edu] On Behalf Of Van Horn, David
Sent: 19 March 2018 17:11
To: ***@gmail.com; Microcontroller discussion list - Public. <***@mit.edu>
Subject: RE: [EE] minimizing capacitance between tracks

Right. If I assume the middle plate is equidistant (probably not true in real life) then we get 2C in series with 2C for the same value.
However, there are fringing effects at the edges of all the plates, and that creates some additional C.
Something’s nagging at me that there’s a way to reduce the total C between the outer plates.

I also have the option of using a grid of dots as the middle “plate”.


From: ***@gmail.com <***@gmail.com>
Sent: Monday, March 19, 2018 11:07 AM
To: Microcontroller discussion list - Public. <***@mit.edu>; Van Horn, David <***@backcountryaccess.com>; Microcontroller discussion list - Public. <***@mit.edu>
Subject: Re: [EE] minimizing capacitance between tracks

David,
The floating layer is like two capacitors electrodes connected in series. So now you get two larger capacitors in series instead of a single one.

My $0.02
Jean-Paul
N1JPL
Sent from Yahoo Mail on Android<https://overview.mail.yahoo.com/mobile/?.src=Android>

On Mon, Mar 19, 2018 at 12:51 PM, Van Horn, David <***@backcountryaccess.com<mailto:***@backcountryaccess.com>> wrote:

A fun thought:

I have a PCB with six layers. I am looking for ways to minimize capacitive coupling between tracks on the top and tracks on the bottom.

If I think of the tracks as parallel plates, and the PCB as the dielectric, then that gives me a certain C, a bit bigger than suggested by the directly overlapping area.

Now what happens if I put a small copper dot, floating, in layer 3 or 4? It seems like this should create a series pair of capacitors of about twice the value, and no net change, but I keep thinking that the end result has to be a little less C than the first case.

Is there something freeware-ish that I can use to model a three (or more) plate capacitor where the middle plates are floating?


--
David VanHorn
Lead Hardware Engineer

Backcountry Access, Inc.
2820 Wilderness Pl, Unit H
Boulder, CO 80301 USA
phone: [phone] x110
email: ***@backcountryaccess.com<mailto:***@backcountryaccess.com><mailto:***@backcountryaccess.com<mailto:***@backcountryaccess.com>>

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[l***@gmail.com]

David,If you use layer 3 or 4, the values will be very close, so the series kind of cancel itself. Better avoid parallel connections. Usage is to use perpendicular flow of traces on nearby layers to minimize interaction.Just another thought,Jean-Paul N1JPL 

Sent from Yahoo Mail on Android

On Mon, Mar 19, 2018 at 12:51 PM, Van Horn, David<***@backcountryaccess.com> wrote:
A fun thought:

I have a PCB with six layers.  I am looking for ways to minimize capacitive coupling between tracks on the top and tracks on the bottom.

If I think of the tracks as parallel plates, and the PCB as the dielectric, then that gives me a certain C, a bit bigger than suggested by the directly overlapping area.

Now what happens if I put a small copper dot, floating, in layer 3 or 4?  It seems like this should create a series pair of capacitors of about twice the value, and no net change, but I keep thinking that the end result has to be a little less C than the first case.

Is there something freeware-ish that I can use to model a three (or more) plate capacitor where the middle plates are floating?


--
David VanHorn
Lead Hardware Engineer

Backcountry Access, Inc.
2820 Wilderness Pl, Unit H
Boulder, CO  80301 USA
phone: [phone]  x110
email: ***@backcountryaccess.com<mailto:***@backcountryaccess.com>

[Richard Prosser]

David,
Can you use guard tracks? - tracks driven at the same voltage as the ones
you're concerned with (e.g. from a buffer). Then place these guard tracks
between the "tracks of concern". Since the adjacent track will be at the
same voltage as the sensitive trace there will be no capacitive loading.
All loading will be be between the 2 guard tracks which doesn't change the
reading.

RP

Post by l***@gmail.com
David,If you use layer 3 or 4, the values will be very close, so the
series kind of cancel itself. Better avoid parallel connections. Usage is
to use perpendicular flow of traces on nearby layers to minimize
interaction.Just another thought,Jean-Paul N1JPL
Sent from Yahoo Mail on Android
I have a PCB with six layers. I am looking for ways to minimize
capacitive coupling between tracks on the top and tracks on the bottom.
If I think of the tracks as parallel plates, and the PCB as the
dielectric, then that gives me a certain C, a bit bigger than suggested by
the directly overlapping area.
Now what happens if I put a small copper dot, floating, in layer 3 or 4?
It seems like this should create a series pair of capacitors of about twice
the value, and no net change, but I keep thinking that the end result has
to be a little less C than the first case.
Is there something freeware-ish that I can use to model a three (or more)
plate capacitor where the middle plates are floating?
--
David VanHorn
Lead Hardware Engineer
Backcountry Access, Inc.
2820 Wilderness Pl, Unit H
Boulder, CO 80301 USA
phone: [phone] x110
backcountryaccess.com>
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View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist
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View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist