[EE] STM32F207 ADC Question

[Jason White]

A footnote (note 2 in attached image) in the STM32F207 datasheet (page 127)
states that a high capacitance at the ADC input pin can reduce conversion
accuracy. How exactly should this be interpreted?

Sure, having a R-C lowpass at the ADC input pin will reduce bandwidth. But
will the capacitance affect the internal operation of the ADC?

[Ryan O'Connor]

You can see Cparasitic is on the same input line as C(ADC). If you have
parasitic capacitance on the input, it will add to the capacitance of
C(ADC) and affect the internal timing circuit of the sample and hold
feature of the ADC. So to answer your question, yes it will affect the
internal operation.

Ryan

Post by Jason White
A footnote (note 2 in attached image) in the STM32F207 datasheet (page 127)
states that a high capacitance at the ADC input pin can reduce conversion
accuracy. How exactly should this be interpreted?
Sure, having a R-C lowpass at the ADC input pin will reduce bandwidth. But
will the capacitance affect the internal operation of the ADC?
--
Jason White
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[Sean Breheny]

I am in the same frame of mind as Jason - I don't see how this could affect
DC accuracy. Yes, the sample and hold circuit will draw pulses of current
from the input but usually external capacitance there HELPS you because it
smooths out the pulses so you don't see as much voltage drop across Rin.
Maybe they are referring to situations where the cap resonates with the
trace inductance and there is ringing after each charging pulse?

Post by Ryan O'Connor
You can see Cparasitic is on the same input line as C(ADC). If you have
parasitic capacitance on the input, it will add to the capacitance of
C(ADC) and affect the internal timing circuit of the sample and hold
feature of the ADC. So to answer your question, yes it will affect the
internal operation.
Ryan
gmail.com>

Post by Jason White
A footnote (note 2 in attached image) in the STM32F207 datasheet (page

127)

Post by Jason White
states that a high capacitance at the ADC input pin can reduce conversion
accuracy. How exactly should this be interpreted?
Sure, having a R-C lowpass at the ADC input pin will reduce bandwidth.

But

Post by Jason White
will the capacitance affect the internal operation of the ADC?
--
Jason White
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[Richard]

Post by Jason White
A footnote (note 2 in attached image) in the STM32F207 datasheet (page 127)
states that a high capacitance at the ADC input pin can reduce conversion
accuracy. How exactly should this be interpreted?
Sure, having a R-C lowpass at the ADC input pin will reduce bandwidth. But
will the capacitance affect the internal operation of the ADC?

I think I have seen an explanation of this before (maybe in a PIC
datasheet?).

The total input capacitance would be affected by the parasitic
capacitance and that would would change the charge time of the ADC
capacitor. For any given input voltage, this will change how many counts
occur for the same sample rate. Thus, note 2 states that the sampling
frequency would have to be reduced to compensate for the difference in
charge time. Lower sample frequency gives more time to charge and more
counts for a given input voltage.

Richard

[Sean Breheny]

But that explanation only makes sense if the parasitic cap were on the ADC
side of the sample-and-hold switch. Once you place it externally, it should
only help, and the sampling frequency or sample-and-hold aperture are
pretty immaterial to it.

Post by Richard

Post by Jason White
A footnote (note 2 in attached image) in the STM32F207 datasheet (page

127)

Post by Jason White
states that a high capacitance at the ADC input pin can reduce conversion
accuracy. How exactly should this be interpreted?
Sure, having a R-C lowpass at the ADC input pin will reduce bandwidth.

But

Post by Jason White
will the capacitance affect the internal operation of the ADC?

I think I have seen an explanation of this before (maybe in a PIC
datasheet?).
The total input capacitance would be affected by the parasitic
capacitance and that would would change the charge time of the ADC
capacitor. For any given input voltage, this will change how many counts
occur for the same sample rate. Thus, note 2 states that the sampling
frequency would have to be reduced to compensate for the difference in
charge time. Lower sample frequency gives more time to charge and more
counts for a given input voltage.
Richard
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[Richard]

Okay, I had to refresh my memory. I couldn't (quickly) find the
Microchip document I thought I had read, but I did find an
STMicroelectronics application note, AN1636, Understanding and
Minimising ADC Conversion Errors. Section 4.5 of that AN talks about the
effect of source capacitance.
The charge time of any input capacitance (including parasitic) needs to
be taken into account. If the input C is not fully charged, the voltage
at the analog input will not be the same as the analog source voltage,
skewing the results.  Thus, the sample time may have to be adjusted to
compensate for the time needed to charge the input C - plus - the time
need to charge the ADC C. Much ore info in the AN.

I don't recall if the list will take a link, but here is the url of the AN:
https://www.st.com/content/ccc/resource/technical/document/application_note/9d/56/66/74/4e/97/48/93/CD00004444.pdf/files/CD00004444.pdf/jcr:content/translations/en.CD00004444.pdf

Richard

Post by Sean Breheny
But that explanation only makes sense if the parasitic cap were on the ADC
side of the sample-and-hold switch. Once you place it externally, it should
only help, and the sampling frequency or sample-and-hold aperture are
pretty immaterial to it.

Post by Richard

Post by Jason White
A footnote (note 2 in attached image) in the STM32F207 datasheet (page

127)

Post by Jason White
states that a high capacitance at the ADC input pin can reduce conversion
accuracy. How exactly should this be interpreted?
Sure, having a R-C lowpass at the ADC input pin will reduce bandwidth.

But

Post by Jason White
will the capacitance affect the internal operation of the ADC?

I think I have seen an explanation of this before (maybe in a PIC
datasheet?).
The total input capacitance would be affected by the parasitic
capacitance and that would would change the charge time of the ADC
capacitor. For any given input voltage, this will change how many counts
occur for the same sample rate. Thus, note 2 states that the sampling
frequency would have to be reduced to compensate for the difference in
charge time. Lower sample frequency gives more time to charge and more
counts for a given input voltage.
Richard
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[Sean Breheny]

Note that this app note makes a distinction between Cadc (section 4.4) and
Cin (section 4.5). It suggests reducing Fsample to help with Cadc and Rin
(internal plus external R) in section 4.4 It suggests reducing Fain (the
SOURCE frequency) to deal with large Cin (section 4.5). These are
completely different effects. The first one (4.4) is the non-obvious one
which is related to the sample and hold cap having to charge. The second
one (section 4.5) is simply saying that external R and C will form a
low-pass filter (duh!) which will filter your signal.

Post by Richard
Okay, I had to refresh my memory. I couldn't (quickly) find the
Microchip document I thought I had read, but I did find an
STMicroelectronics application note, AN1636, Understanding and
Minimising ADC Conversion Errors. Section 4.5 of that AN talks about the
effect of source capacitance.
The charge time of any input capacitance (including parasitic) needs to
be taken into account. If the input C is not fully charged, the voltage
at the analog input will not be the same as the analog source voltage,
skewing the results. Thus, the sample time may have to be adjusted to
compensate for the time needed to charge the input C - plus - the time
need to charge the ADC C. Much ore info in the AN.
https://www.st.com/content/ccc/resource/technical/
document/application_note/9d/56/66/74/4e/97/48/93/CD00004444.pdf/files/
CD00004444.pdf/jcr:content/translations/en.CD00004444.pdf
Richard

Post by Sean Breheny
But that explanation only makes sense if the parasitic cap were on the

ADC

Post by Sean Breheny
side of the sample-and-hold switch. Once you place it externally, it

should

Post by Sean Breheny
only help, and the sampling frequency or sample-and-hold aperture are
pretty immaterial to it.

Post by Richard

Post by Jason White
A footnote (note 2 in attached image) in the STM32F207 datasheet (page

127)

Post by Jason White
states that a high capacitance at the ADC input pin can reduce

conversion

Post by Sean Breheny

Post by Richard

Post by Jason White
accuracy. How exactly should this be interpreted?
Sure, having a R-C lowpass at the ADC input pin will reduce bandwidth.

But

Post by Jason White
will the capacitance affect the internal operation of the ADC?

I think I have seen an explanation of this before (maybe in a PIC
datasheet?).
The total input capacitance would be affected by the parasitic
capacitance and that would would change the charge time of the ADC
capacitor. For any given input voltage, this will change how many counts
occur for the same sample rate. Thus, note 2 states that the sampling
frequency would have to be reduced to compensate for the difference in
charge time. Lower sample frequency gives more time to charge and more
counts for a given input voltage.
Richard
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[RussellMc]

Post by Richard
Minimising ADC Conversion Errors. Section 4.5 of that AN talks about the
effect of source capacitance.
https://www.st.com/content/ccc/resource/technical/
document/application_note/9d/56/66/74/4e/97/48/93/CD00004444.pdf/files/
CD00004444.pdf/jcr:content/translations/en.CD00004444.pdf
Useful reference.

They are talking about the settling time of the applied signal and the
affects of t = Rexternal x C external on this.
ie if you want to measure a voltage do your best to ensure that the voltage
is what's on the pin when you measure it.
[ :-) ].

I was interested in 4.6

" 4.6 EFFECT OF INJECTION CURRENT

ST microcontrollers have robust tolerance of additional leakage current
introduced on analog input signals as an effect of negative injection
current. Negative injection current on any analog pin (or closely placed
digital input pin) may introduce leakage current into the ADC input. The
worst case is the adjacent analog channel. Negative injection current is
introduced when Vin < Vss. ..."

While this effect is well enough known, I don't recall this being put so
clearly elsewhere as it is in this section.

I also note:

" ... Positive injection current is introduced when VIN > VDD. Therefore
current flows into the I/O pin. Positive injection current within the limit
does not cause any loss of accuracy. ..."

Within the limit?


R





Richard

Post by Richard

Post by Sean Breheny
But that explanation only makes sense if the parasitic cap were on the

ADC

Post by Sean Breheny
side of the sample-and-hold switch. Once you place it externally, it

should

Post by Sean Breheny
only help, and the sampling frequency or sample-and-hold aperture are
pretty immaterial to it.

Post by Richard

Post by Jason White
A footnote (note 2 in attached image) in the STM32F207 datasheet (page

127)

Post by Jason White
states that a high capacitance at the ADC input pin can reduce

conversion

Post by Sean Breheny

Post by Richard

Post by Jason White
accuracy. How exactly should this be interpreted?
Sure, having a R-C lowpass at the ADC input pin will reduce bandwidth.

But

Post by Jason White
will the capacitance affect the internal operation of the ADC?

I think I have seen an explanation of this before (maybe in a PIC
datasheet?).
The total input capacitance would be affected by the parasitic
capacitance and that would would change the charge time of the ADC
capacitor. For any given input voltage, this will change how many counts
occur for the same sample rate. Thus, note 2 states that the sampling
frequency would have to be reduced to compensate for the difference in
charge time. Lower sample frequency gives more time to charge and more
counts for a given input voltage.
Richard
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[Manu Abraham]

AFAICS, the footnote is self explanatory. "To remedy this fADC should
be reduced".
The larger the capacitance, larger the acquisition time, or in other
words time taken
to charge that capacitor.

To maintain the nyquist sampling rate, you need to reduce the sampling
frequency,
eventually affecting bandwidth, as you guessed.

Cheers,

Manu



On Wed, Aug 22, 2018 at 1:36 AM, Jason White

Post by Jason White
A footnote (note 2 in attached image) in the STM32F207 datasheet (page 127)
states that a high capacitance at the ADC input pin can reduce conversion
accuracy. How exactly should this be interpreted?
Sure, having a R-C lowpass at the ADC input pin will reduce bandwidth. But
will the capacitance affect the internal operation of the ADC?
--
Jason White
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist