Dual Core dsPICs

[AB Pearce - UKRI STFC]

For those who have not been following the noise on the Microchip Forums, the initial model of dual core dsPICs is out.

https://www.microchip.com/forums/m1026362.aspx

Work your way through and there are links to the data sheet and errata as well as a link to the Microchip Direct page to purchase them. Note that only the most limited temperature range device is available immediately.

They are also listed on Farnell (Onecall, element14, whatever else their favourite name of the year is) (link in above link). The UK price from Farnell is about the same as buying from Microchip Direct.

[AB Pearce - UKRI STFC]

Try again with tag ...

Post by AB Pearce - UKRI STFC
For those who have not been following the noise on the Microchip Forums,
the initial model of dual core dsPICs is out.
https://www.microchip.com/forums/m1026362.aspx
Work your way through and there are links to the data sheet and errata as
well as a link to the Microchip Direct page to purchase them. Note that only
the most limited temperature range device is available immediately.
They are also listed on Farnell (Onecall, element14, whatever else their
favourite name of the year is) (link in above link). The UK price from Farnell is
about the same as buying from Microchip Direct.
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[Jason White]

Neat!

On Fri, Jun 22, 2018 at 10:02 AM, AB Pearce - UKRI STFC <

Post by AB Pearce - UKRI STFC
Try again with tag ...

Post by AB Pearce - UKRI STFC
For those who have not been following the noise on the Microchip Forums,
the initial model of dual core dsPICs is out.
https://www.microchip.com/forums/m1026362.aspx
Work your way through and there are links to the data sheet and errata as
well as a link to the Microchip Direct page to purchase them. Note that

only

Post by AB Pearce - UKRI STFC
the most limited temperature range device is available immediately.
They are also listed on Farnell (Onecall, element14, whatever else their
favourite name of the year is) (link in above link). The UK price from

Farnell is

Post by AB Pearce - UKRI STFC
about the same as buying from Microchip Direct.
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[John J. McDonough]

Post by AB Pearce - UKRI STFC
For those who have not been following the noise on the Microchip Forums, the initial model of dual core dsPICs is out.
https://www.microchip.com/forums/m1026362.aspx

OK, so I had to get some to play with. My discoveries so far:

https://elmer166.blogspot.com/2018/07/dspic33ch128mp505.html

--McD

[Jason White]

Neat! Thanks John for posting.

Post by AB Pearce - UKRI STFC

Post by AB Pearce - UKRI STFC
For those who have not been following the noise on the Microchip Forums,

the initial model of dual core dsPICs is out.

Post by AB Pearce - UKRI STFC
https://www.microchip.com/forums/m1026362.aspx

https://elmer166.blogspot.com/2018/07/dspic33ch128mp505.html
--McD
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[Harold Hallikainen]

Great writeup!I think FIFO communications between the two cores would be
interesting. I do a lot of FIFO communications between tasks in a PIC32.

Thanks!

Harold

Post by John J. McDonough

Post by AB Pearce - UKRI STFC
For those who have not been following the noise on the Microchip Forums,
the initial model of dual core dsPICs is out.
https://www.microchip.com/forums/m1026362.aspx

https://elmer166.blogspot.com/2018/07/dspic33ch128mp505.html
--McD
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist

[John J. McDonough]

Post by Harold Hallikainen
Great writeup!I think FIFO communications between the two cores would be
interesting.

Thanks.

So I went and tried out the FIFO and if anything it is even easier than
the mailbox. I added a couple of code snippets to the blog, but
basically, there is a receive and send enable bit to set, and then it is
simply a matter of reading or writing to the FIFO register.

Of course there are overflow, empty, etc. status bits.

--McD

Post by Harold Hallikainen
I do a lot of FIFO communications between tasks in a PIC32.
Thanks!
Harold

Post by John J. McDonough

Post by AB Pearce - UKRI STFC
For those who have not been following the noise on the Microchip Forums,
the initial model of dual core dsPICs is out.
https://www.microchip.com/forums/m1026362.aspx

https://elmer166.blogspot.com/2018/07/dspic33ch128mp505.html
--McD
--
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View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist

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FCC Rules Updated Daily at http://www.hallikainen.com
Not sent from an iPhone.

[Clint Jay]

Oh nice, so the _program_slave argument takes a processor number argument
which could indicate that there may be multi slave products in the offing.

Post by AB Pearce - UKRI STFC

Post by AB Pearce - UKRI STFC
For those who have not been following the noise on the Microchip Forums,

the initial model of dual core dsPICs is out.

Post by AB Pearce - UKRI STFC
https://www.microchip.com/forums/m1026362.aspx

https://elmer166.blogspot.com/2018/07/dspic33ch128mp505.html
--McD
--
http://www.piclist.com/techref/piclist PIC/SX FAQ & list archive
View/change your membership options at
http://mailman.mit.edu/mailman/listinfo/piclist

[AB Pearce - UKRI STFC]

Oh nice, so the _program_slave argument takes a processor number argument which
could indicate that there may be multi slave products in the offing.

Yes, I have noticed that too. But the other interesting thing with the current chips is that you appear to be able to have multiple pieces of code that can be loaded (as noted in the write up) so you could have a separate diagnostic module to the normal run module, assuming you can get it all in the master EEPROM, along with its code.

But what I could also see happening is having a large EEPROM chip, either I2C or SPI, connected which has the slave code in it and then a tiny bootloader in the master code that gets loaded into the slave to download the code from the external EEPROM. You could then have multiple tiny bootloaders that use different offsets into the external EEPROM to load different modules. Another possibility with having external EEPROM would be doing code overlays, so you could overlay part of the code for a calibration mode, for example.